1. Field of the Invention
The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor chip having bond pads and to a semiconductor package.
2. Description of the Related Art
The industry is expending significant effort toward forming smaller and thinner chips to meet the demand for high packing density in high-speed, multi-functional semiconductor devices. To reduce chip size, the size of bond pads as well as the pitch between bond pads should be reduced.
Conventional semiconductor chips have either a center pad-type or a peripheral pad-type structure. FIG. 1 is a plan view of a conventional center pad-type semiconductor chip. FIG. 2 is a cross-sectional view of the conventional center pad-type chip taken along line 2-2 of FIG. 1. FIG. 3 is a plan view of a conventional peripheral pad-type semiconductor chip. FIG. 4 is a cross-sectional view of the conventional peripheral pad-type chip taken along the line 4-4 of FIG. 3.
Referring to FIGS. 1 and 2, a center pad-type semiconductor chip 110 comprises a peripheral circuit region Aperi for forming bond pads 112 and cell regions Acell1 and Acell2. The peripheral circuit region Aperi is formed in the center region of a semiconductor substrate 111. The cell regions Acell1 and Acell2 are formed on the sides of the peripheral circuit region Aperi.
Referring to FIGS. 3 and 4, a peripheral pad-type semiconductor chip 120 comprises peripheral circuit regions Aperi1 and Aperi2 and a cell region Acell. The cell region Acell is formed in the center region of the semiconductor substrate 121. The peripheral circuit regions Aperi1 and Aperi2 are formed on the sides of the cell region Acell. Referring to FIGS. 2 and 4, a passivation layer 113, 123 is formed over the cell regions and the peripheral circuit regions in both the center and peripheral pad-type chips.
In the conventional semiconductor chips 110, 120 of FIGS. 1 through 4, an additional chip area is needed in peripheral circuit regions for forming bond pads 112, 122. As a result, the ability to reduce the size of the conventional semiconductor chips 110 and 120 is limited in both chip pad types.
Furthermore, it has been difficult to reduce the bond pad size and the pitch between the bond pads 112, 122 in the conventional semiconductor chips 110 and 120. This is because the bond pads 112, 122 must have a designed minimum size and pitch for electric die sorting (EDS) and to form electrical interconnections.
The ability to reduce the size of a multi-chip package (MCP) including multiple conventional semiconductor chips in a single body package is also limited due to problems such as the difficulty of stacking center pad-type chips on chips of the same or similar types. That is, wire bonding can be complicated and difficult due to long loop wires in such cases.
Accordingly, there is a need for a smaller semiconductor chip that can easily form an MCP without suffering from the problems mentioned above.